1. Field of the Invention
The present invention relates to electrochemical deposition of a metal.
2. Description of the Related Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to less than 250 nanometers, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many conventional deposition processes have difficulty filling structures where the aspect ratio exceeds 4:1, and particularly where the aspect ratio exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized features having high aspect ratios wherein the ratio of feature height to feature width can be 4:1 or higher. Additionally, as the feature widths decrease, the device current remains constant or increases, which results in an increased current density in the feature.
Elemental aluminum (Al) and its alloys have been the traditional metals used to form lines and plugs in semiconductor processing because of aluminum's perceived low electrical resistivity, its superior adhesion to silicon dioxide (SiO2), its ease of patterning, and the ability to obtain it in a highly pure form. However, aluminum has a higher electrical resistivity than other more conductive metals such as copper, and aluminum also can suffer from electromigration leading to the formation of voids in the conductor.
Copper and its alloys have lower resistivities than aluminum and significantly higher electromigration resistance as compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Copper also has good thermal conductivity and is available in a highly pure state. Therefore, copper is becoming a choice metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features, such as 4:1, having 0.35 μm (or less) wide vias are limited. As a result of these process limitations, plating, which had previously been limited to the fabrication of lines on circuit boards, is just now being used to fill vias and contacts on semiconductor devices.
Metal electroplating is generally known and can be achieved by a variety of techniques. A typical method generally comprises depositing a barrier layer over the feature surfaces, depositing a conductive metal seed layer, preferably copper, over the barrier layer, and then electroplating a conductive metal over the seed layer to fill the structure/feature. The deposited layers and the dielectric layers can be planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Electroplating or electrochemical deposition is being projected as an economical and viable solution for future copper interconnect needs. FIG. 1 is a simplified sectional view of a fountain plater 10. Generally, the fountain plater 10 includes an electrolyte container 12 having a top opening, a substrate holder 14 disposed above the electrolyte container 12, an anode 16 disposed at a bottom portion of the electrolyte container 12 and a contact ring 20 contacting the substrate 22. A plurality of grooves 24 are formed in the lower surface of the substrate holder 14. A vacuum pump (not shown) is coupled to the substrate holder 14 and communicates with the grooves 24 to create a vacuum condition capable of securing the substrate 22 to the substrate holder 14 during processing. The contact ring 20 comprises a plurality of metallic or semi-metallic contact pins 26 distributed about the peripheral portion of the substrate 22 to define a central substrate plating surface. The plurality of contact pins 26 extend radially inwardly over a narrow perimeter portion of the substrate 22 and contact a conductive seed layer of the substrate 22 at the tips of the contact pins 26. A power supply 30 is electrically connected to the anode 16 and to the pins 26 thereby providing an electrical bias to the substrate 22. The substrate 22 is positioned above the cylindrical electrolyte container 12 and electrolyte flow impinges perpendicularly on the substrate plating surface during operation of the cell 10.
The electroplating process is typically carried out by applying a constant current density across the substrate plating surface. For example, a constant current density between about 1 and about 60 milliamperes/cm2 (mA/cm2), e.g., about 40 mA/cm2, may be applied across the substrate plating surface to cause deposition thereon. Since the deposition rate is generally a function of the current density applied over the substrate plating surface, the current density is typically increased, e.g., greater than about 40 mA/cm2, to provide faster deposition and increased substrate throughput.
One particular problem encountered in existing electroplating processes is that these electroplating processes have not been able to provide void-free or seam-free fill of high aspect ratio structures. FIG. 2 illustrates a typical deposition result of a high aspect ratio feature 202 on a substrate 200 wherein the mouth/opening 206 of the structure 202 closes off due to overhang or excess deposition of copper at the mouth/opening 206 of the structure 202 also known as crowning. It has been observed that the deposited metal 210 tends to grow much faster at the mouth or opening 206 of the structure 202, resulting in crowning at the mouth/opening 206 of the structure 202 and leaving a void 204 inside the structure 202, as well as a seam 208. The crowning is accelerated by an increase of the current densities during electroplating, thereby causing even larger voids. It has been observed that voids are also formed in the interconnect features due to grain mismatches from the deposition growth. Furthermore, the presence of the seam 208 may result in void formation during subsequent processing such as substrate annealing.
Therefore, there is a need for a method of electrochemical deposition of a metal into high aspect ratio structures on a substrate that provides void-free and seam-free fill of high aspect ratio structures.